This disclosure relates to a semiconductor package and a method of fabricating the same and, more particularly, to a semiconductor package including a semiconductor chip mounted by a flip chip bonding method and a method of fabricating the same.
It is a recent trend to inexpensively fabricate electronic products of lightness, small size, high speed, multi-function, and high performance. A packaging technique used to fabricate such products is an important technique for achieving this trend. Recently, a chip scale package (CSP) technique has been suggested. The CSP technique may provide a small semiconductor package of a semiconductor chip scale.
Often, a mass storage of the semiconductor package is demanded in combination with a small size of the semiconductor package. However, a technique capable of integrating a lot of cells in a limited space of the semiconductor chip is needed for increasing a memory capacity of the semiconductor package. This technique may require a high level technique for forming fine patterns and a long developing time. Thus, techniques of highly integrating a semiconductor package using a semiconductor chip and/or a semiconductor package have been developed for easily realizing mass storage semiconductor packages. For example, various researches have been conducted for a multi-chip stacked package including three-dimensionally stacked semiconductor chips or a stack type semiconductor package including three-dimensionally stacked semiconductor packages.